In a prior microprocessor based system having memory, a microprocessor, as well as other circuitry, it is necessary to have clock or timing signals for various uses. For instance, when a microprocessor accesses a DRAM (i.e., dynamic random access memory) in the system, many clock signals are required from the microprocessor to latch addresses, decode the addresses, access the memory array, precharge nodes, control refreshing, etc.
The advances in the microprocessor technologies have led to the creation of high speed and high performance microprocessors. However, interfacing such a high speed, high performance microprocessor to a DRAM array requires the microprocessor to analyze many timings, to examine refresh cycle effects on bus timing, and to note minimum and maximum signal widths, which adversely affects the speed and performance of the microprocessor.
One prior solution to these problems is to design a DRAM controller that interfaces with the microprocessor and the DRAM device. A prior DRAM controller typically provides complete control and timing for the DRAM device. The microprocessor interfaces with the DRAM controller. Other system bus masters may also interface with the DRAM controller. The DRAM controller decodes CPU to DRAM access commands, translates the microprocessor address to the proper multiplied DRAM row and column address, and generates the proper DRAM control timing signals required to successfully complete the DRAM access cycle.
The DRAM controller typically operates at the same frequency as that of the microprocessor and other system bus masters. This is due to the fact that the DRAM controller typically receives the same clock signal as that of the microprocessor and the system bus masters. FIG. 1 illustrates a typically prior art clock supply arrangement for a computer system having the DRAM controller.
As can be seen from FIG. 1, computer system 5 includes a clock source 6 that generates a clock signal CLK. The clock signal CLK is supplied to each of a DRAM controller 7, a CPU 8, and a bus controller 9 of computer system 5. In other words, DRAM controller 7, CPU 8, bus controller 9 all receive the same clock signal CLK from clock source 6.
One disadvantage of this scheme is the DRAM access latency. Due to typical DRAM AC parameters, certain DRAM access latencies (i.e., delays) are incurred in the DRAM controller upon completion of a DRAM access cycle. Typically, cycle decoding, address translation, and control signal generation all generate delays. The delays are typically measured as wait states at the microprocessor (i.e., CPU) or the bus controller, which affect the speed and performance of the microprocessor and the bus controller.
Another disadvantage of the scheme is that the DRAM controller is typically unable to operate synchronously with the microprocessor and other system masters at the clock signal CLK. This is due to the fact that different delays may be incurred to the clock signal CLK supplied to each of the DRAM controller, the microprocessor, and the bus controller. Typically, the DRAM controller has a CPU interface circuit that interfaces with the external microprocessor and a bus controller interface circuit that interfaces with the external bus controller. The DRAM controller includes a clock generation circuit that receives the CLK clock signal and supplies the clock signal to the interface circuits of the DRAM controller.
Due to wafer processing variations, power supply variations, operation temperature variations, and other variations, substantial variations exist in the delays of the clock signal CLK occurred in the DRAM controller, in the microprocessor, and in the bus controller. In this case, the clock signal CLK received in the CPU interface circuit of the DRAM controller has a substantially different delay than that in the microprocessor. This typically causes the two circuits not to operate synchronously with each other. In this case, the microprocessor has to wait in order to follow the operation of the DRAM controller, or vice versa.
Typically, all the input signals to the DRAM controller are made to synchronize with the clock signal CLK received at the DRAM controller. This is typically done by having the DRAM controller wait for a couple of clock cycles before it responds to the input signals. Because the signal delay generated by the DRAM controller is different from that generated by the microprocessor or bus controller, it is typically difficult to synchronize the DRAM controller with the external microprocessor and bus controller.